One-line summary
The 6th RISC-V China Summit runs from October 18 to 20, 2026 at the Shenzhen Convention & Exhibition Center (Futian), with industry players including DAMO Academy, ESWIN Computing, SpacemiT, RISC-V China and Tenstorrent in attendance; the RISC-V open instruction set architecture has been placed on China's chip self-innovation agenda as an open ISA path alongside x86 and Arm.
Background
RISC-V is an open, royalty-free instruction set architecture (ISA): unlike x86 or Arm, its base specification can be freely obtained and used. According to Xinhua News Agency, the 6th RISC-V China Summit is scheduled for October 18-20, 2026 at the Shenzhen Convention & Exhibition Center (Futian), and is described as one of the world's three major RISC-V summits and the highest-profile professional conference in China.
What Is RISC-V
RISC-V originated from a 2010 research project at the University of California, Berkeley. It follows the reduced instruction set computing (RISC) design, with a freely open, modularly extensible base instruction set. In January 2024, RISC-V International announced that the base instruction set specification had been approved as the international standard ISO/IEC 23575:2023. Any organization or individual can design processors based on this architecture without paying licensing fees, making it the core of the open-chip ecosystem.
6th RISC-V China Summit Highlights
The summit runs for 3 days from October 18 to 20, 2026 in Shenzhen. According to Xinhua News Agency, industry players including DAMO Academy, ESWIN Computing, SpacemiT, RISC-V China and Tenstorrent will gather. The summit covers chip design, toolchains, operating systems, AI acceleration and industry applications, serving as the main window on China's RISC-V ecosystem progress.
Policy and Industrial Support in China
RISC-V has been placed on China's chip self-innovation strategic agenda. The Ministry of Industry and Information Technology, the Ministry of Science and Technology, the National Development and Reform Commission and multiple local governments continue to increase support for open chips and the RISC-V ecosystem; Shanghai, Shenzhen, Beijing and Guangzhou have issued integrated circuit industry plans that list RISC-V as a key development direction.
Ecosystem and Common Misconceptions
- Open ISA vs open chip: RISC-V opens the instruction set specification; specific chip products are still designed and implemented by individual vendors, and not all RISC-V chips are open source.
- Ecosystem participants: RISC-V International members span vendors and research institutions worldwide; the summit attendees are only part of the ecosystem.
- Applications: RISC-V already covers embedded, IoT, edge computing and AI acceleration scenarios; specific product forms follow vendor announcements.