One-sentence summary
On November 10, 2026, MemryX AI, a fabless semiconductor company based in Ann Arbor, Michigan, unveiled MX3+, its next-generation edge AI inference accelerator. The company claims up to 10 times the peak AI compute and nearly 10 times the on-chip memory of MX3 within the same low-power envelope; a 16-chip configuration targets more than 1 POPS and 2.16 GB of distributed on-chip memory, with engineering samples planned for late 2027 and volume production for mid-2028.
Event overview
On November 10, 2026, MemryX AI announced MX3+ in a press release distributed by PR Newswire. MemryX is a fabless semiconductor company developing efficient, scalable AI inference silicon for edge devices, industrial systems and data-center infrastructure. MX3+ is the successor platform to MX3, which the company describes as production-proven.
The central claim is quantitative: MX3+ is designed to deliver up to 10 times more peak AI compute and nearly 10 times more on-chip memory than MX3 while staying within the same low-power operating envelope. The words "up to" and "nearly" matter: these are design targets for a product that has not yet shipped, not measured results from production hardware.
MX3+ keeps the multi-chip approach established with MX3. Multiple accelerators operate as a unified logical device, and planned configurations scale from a single chip to 16 chips. The 16-chip design targets more than 1 POPS, or one peta-operation per second of peak AI compute, with 2.16 GB of distributed on-chip memory.
The timeline is explicit: engineering samples are targeted for late 2027 and volume production for mid-2028. MemryX is accepting early-access requests from selected strategic partners and enterprise customers to co-validate pre-production hardware and software.
Key facts
| Item | What MemryX disclosed |
|---|---|
| Announcement date | November 10, 2026 (PR Newswire) |
| Company | MemryX AI, headquartered in Ann Arbor, Michigan |
| Product | MX3+, next-generation edge AI inference accelerator |
| Compute target | Up to 10x the peak AI compute of MX3 |
| Memory target | Nearly 10x the on-chip memory of MX3 |
| Power target | Same low-power operating envelope as MX3 |
| Scaling | Single chip to 16 chips, operating as one logical device |
| 16-chip configuration | More than 1 POPS peak AI compute; 2.16 GB distributed on-chip memory |
| Target workloads | Higher-resolution vision, transformers, small language models, VLAs, hybrid architectures, multi-model pipelines |
| Target deployments | Edge devices, industrial systems, high-density inference infrastructure |
| Developer tool | MemryX Neural Compiler automatically maps models across accelerators |
| Sampling | Engineering samples targeted for late 2027 |
| Volume production | Targeted for mid-2028 |
| Next platform | MX4, aimed at multimodal and large language model inference |
1 POPS is built from 16 chips
POPS stands for peta-operation per second. One POPS equals 10 to the 15th power operations per second. It is a peak-compute unit, not measured model throughput: vendors typically derive peak numbers from multiply-accumulate units and clock frequency, while real inference performance depends on model structure, memory bandwidth, compiler efficiency and batching.
The 1 POPS figure belongs to the 16-chip configuration, not a single chip. MemryX describes 16 accelerators operating as one logical device, with more than 1 POPS of peak AI compute and 2.16 GB of distributed on-chip memory. Averaged across the 16 chips, that is about 62.5 TOPS and 135 MB of on-chip memory per chip; this is arithmetic on the disclosed totals, not a published per-chip specification.
The key enabler is the "unified logical device" design. MemryX's distributed dataflow architecture lets multiple accelerators work together without the host processor managing each chip, and the Neural Compiler automatically maps a neural network across the available accelerators. Developers do not have to partition a model by hand when they add chips.
The cost of this approach is compiler and interconnect complexity. As chip count rises, model partitioning, data movement and synchronization overhead rise with it. MemryX has not published interconnect bandwidth, latency or energy-efficiency data for the 16-chip configuration, so the share of the 1 POPS peak that a real model can reach cannot be determined.
Why the edge bottleneck is on-chip memory
The common bottleneck in edge AI is not peak compute but data movement. Model weights, activations and high-resolution inputs move repeatedly between the processor and external memory, and the power and latency of that movement consume the compute gain. MemryX's answer is near-memory dataflow: keep model data as close to the compute units as possible and minimize movement.
MX3+ raises on-chip memory to nearly 10 times the MX3 level so that larger models and higher-resolution inputs stay on chip. The target workloads MemryX lists include higher-resolution vision, transformers, small language models, vision-language-action models (VLAs), hybrid architectures and more complex multi-model pipelines. All of them are sensitive to memory capacity and bandwidth.
MemryX also emphasizes low, predictable latency at batch size one. Edge devices usually handle one request at a time and cannot rely on large batches to raise throughput, so single-request latency and energy efficiency matter more than peak compute. MX3+ is designed for predictable low latency rather than maximum throughput.
On-chip memory and external memory are different things. The 2.16 GB figure is distributed on-chip memory across 16 chips, not the memory of a single chip and not total system memory. Whether a model fits entirely on chip depends on model size, quantization and the compiler's partitioning strategy; MemryX has not published per-chip on-chip memory capacity or bandwidth.
The MX3 and MX4 roadmap
MX3 is MemryX's production edge AI accelerator; its official product page lists a power range of 200 mW to 3 W. MX3+ is positioned to raise peak compute and on-chip memory by nearly 10 times within the same power range, which implies a large increase in compute density per watt, though MemryX has not published a TOPS/W figure.
MX3+ retains MX3's instruction set, compiler and multi-chip scaling model, so customers can move from embedded devices to high-density inference infrastructure within one development flow. In the press release, President and CEO Ross Jatou says customers will be able to use the same architectural foundation across embedded devices, industrial systems and high-density inference infrastructure, and move complex workloads from development to volume production.
MX4 is a farther-out platform. MemryX says the capabilities introduced in MX3+ will carry forward into MX4, which targets advanced multimodal and large language model inference. MX3+ is therefore a scaled-up version of the current architecture, while MX4 is the next architecture for new workloads; the two are a relay in time, not substitutes for each other.
What late 2027 and mid-2028 mean
Engineering samples in late 2027 and volume production in mid-2028 mean MX3+ is a design target today, not a product a customer can order. For customers, the work from 2026 to 2027 is early access, pre-production hardware validation and software-stack adaptation. For MemryX, that period covers tape-out, yield ramp, compiler optimization and customer design-ins.
That timeline is long by edge AI chip standards. Moving from engineering samples to volume production usually takes 12 to 18 months to resolve silicon defects, packaging, power and reliability issues. The roughly six months MemryX allows between late 2027 and mid-2028 is tight. The company has not disclosed tape-out status, yield targets or first customers, so the schedule cannot be verified.
For buyers, the confirmed facts are that MX3 remains in production and MX3+ is the upgrade path after 2027. A project that needs delivery in 2026 or 2027 should use MX3 or another production chip as its baseline; a project planned for 2028 can begin evaluating MX3+'s 10x compute and memory gains.
Impact and limits
First, edge AI competition is shifting from single-chip compute to the balance of compute, memory and power. MX3+'s main selling point is not the 1 POPS peak figure but the nearly 10x on-chip memory within the same low-power envelope. For edge devices, memory capacity often decides whether a model can run at all.
Second, a unified logical device lowers the barrier to scaling but raises compiler complexity. Automatic mapping through the Neural Compiler is a MemryX differentiator; real-world results depend on operator support, quantization precision and multi-chip interconnect efficiency, and no third-party benchmark has been published.
Third, the timeline is the largest uncertainty. Late 2027 sampling and mid-2028 volume production are more than a year away, and architecture, process and customer requirements can change in that window. MemryX has not disclosed tape-out or yield information, so this site cannot verify the schedule.
Fourth, 1 POPS is a peak figure. MemryX has not published throughput, latency or power data for specific models such as ResNet, YOLO or transformers, nor has it published performance per watt. The 1 POPS number cannot be converted directly into frame rates or token-generation speed for a real application.
The limits are clear: MX3+'s compute, memory, power and timeline are company design targets; per-chip specifications, interconnect bandwidth, pricing, energy efficiency and customer names are undisclosed. This site reports only the published figures and does not estimate undisclosed performance.